(1.) Field of the Invention
This invention relates to the passivation of exposed copper in a copper damascene structure and more specifically to dielectric layers used as an etch stop as well as passivation for exposed copper.
(2.) Background of the Invention
As the cross section area of conductors in integrated circuits continue to shrink the conductivity of the conductor material becomes increasingly important. While aluminum has long been the conductor material of choice in integrated circuits, materials having greater conductivity such as gold, silver, copper, or the like are used with increasing frequency.
These metals have not had more widespread use because they suffer from a number of disadvantages such as the formation of undesirable intermetallics and high diffusion rates. Copper has the additional disadvantage of being easily oxidized at relatively low temperatures. One particular problem of this easy oxidation of copper is that conventional photoresist processing can not be used to pattern the copper. At the end of the patterning process using photoresist the photoresist must be removed by heating it in a highly oxidizing environment which also oxidizes the copper conductors. One solution to this problem is the Damascene process for forming copper conductors.
Although the damascene process for forming copper conductors avoids the use of photoresist to pattern the copper conductors, exposed copper remains after the patterning process. Passivation layers over the exposed copper are required to avoid oxidation of the exposed copper or contamination of the exposed copper during subsequent process steps or during wafer storage.
U.S. Pat. No. 5,744,376 to Chan et al. describes a method of forming copper interconnections using a damascene structure with provisions to prevent both copper diffusion and copper oxidation.
U.S. Pat. No. 5,693,563 to Teong describes a method of forming copper interconnections using an etch stop in a double damascene structure having provision to prevent both copper diffusion and oxidation.
U.S. Pat. No. 5,677,244 to Venkatraman describes damascene structure using a copper alloy as a conductor material.
U.S. Pat. No. 5,602,053 to Zheng et al. describes a method of forming a dual damascene structure using copper conductors and a pair of alternating layers of silicon nitride and amorphous silicon sandwiched between two dual damascene conductors.
Patent application Ser. No. 09/349,847, Filed Jul. 8, 1999, entitled "METHOD OF FABRICATING A DAMASCENE STRUCTURE FOR COPPER MEDULLIZATION" and assigned to the same Assignee describes a method of forming a copper damascene structure over a filled contact hole and the use of a sacrificial dielectric layer to protect an etch stop layer during chemical mechanical polishing.
Patent application Ser. No. 09/349,849, Filed Jul. 8, 1999, entitled "ROBUST POST Cu--CMP IMD PROCESS" and assigned to the same Assignee describes methods of cleaning exposed copper between the steps of chemical mechanical polishing and intermetal dielectric deposition.